1. Field of the Invention
The present invention relates to an electrically-rewritable nonvolatile semiconductor memory device, and more specifically to a booster circuit thereof.
2. Background Art
In a nonvolatile semiconductor memory device capable of electrically erasing, writing, and reading data, it is required to apply a high voltage equal to or higher than a supply voltage to a selected memory cell in an erase and write operation and therefore a boost voltage which is a desired high voltage is generated using a booster circuit including a booster unit and a control system thereof.
In general, a driving force of the booster circuit depends on the amplitude of boosting clock pulses. Moreover, the erase and write operation on the nonvolatile memory is sometimes performed by selecting different numbers of memory cells such as, for example, memory cells in units of a word, a page composed of a plurality of words, or a sector or in a lump of all regions, and the like. Therefore, a load capacity depends on the number of selected memory cells.
A boost voltage arrival time depends on a correlation between the driving force of the booster circuit and the load capacity. The greater the driving force of the booster circuit is, the shorter the boost voltage arrival time is. The larger the load capacity is, the longer the boost voltage arrival time is. Specifically, the boost voltage arrival time varies according to the amplitude of boosting clock pulses or the number of selected memory cells. If the boost voltage arrival time is too short, it causes an increase in the time for which an intense electric field is applied, which accelerates the reliability degradation of the memory cells. Contrary to this, if the boost voltage arrival time is too long, it causes a decrease in the time for which the electric field strength required for rewriting is applied to the memory cells, which leads to insufficient rewriting.
To solve this problem, there is proposed a technique described below (for example, see Patent Document 1). In Patent Document 1, the boost voltage arrival time is monitored in real time and compared with the time previously recorded in a ROM. Then, if the boost voltage arrival time is short, the amplitude of the clock pulses is decreased to reduce the capability of boosting of the booster circuit for adjustment to correct the short boost voltage arrival time. If the boost voltage arrival time is long, the amplitude of the clock pulses is increased to enhance the capability of boosting of the booster circuit for adjustment to correct the long boost voltage arrival time. Thereby, appropriate boost voltage arrival time is achieved by adjusting the driving force of the booster circuit so that the driving force of the booster circuit is appropriate for the load capacity.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2005-117773